1. Field of the Invention
The present invention relates to methods of manufacturing semiconductor devices and apparatus therefor, and more particularly, to a method of manufacturing a capacitor of a semiconductor device and an apparatus for forming a dielectric layer of the capacitor.
2. Description of the Related Art
According to a conventional method of manufacturing capacitors of semiconductor devices, dielectric layers are deposited using a source gas along with a reactant gas such as O2, H2O, H2O2, and N2O. Also, as shown in FIG. 1, to improve electrical properties, multiple dielectric layers are deposited (D1, D2, . . . , and Dn) between steps of forming a first electrode (1) and a second electrode (2), and multiple curing processes are performed (C1, C2, . . . , and Cn) between every two steps of forming dielectric layers.
For example, in the conventional method of forming a dielectric layer of a capacitor used in a stand-alone memory or an embedded memory a deposition process is performed twice and a curing process is performed twice. That is, as shown in FIG. 2, two dielectric layers DL1 and DL2 are formed between two electrodes 15 and 30. Assuming, for convenience, that the thickness of the first dielectric layer DL1 is St1, the thickness of the second dielectric layer DL2 is St2, and the sum of the thicknesses of the two dielectric layers DL1 and DL2 is t1(St1+St2).
Meanwhile, a dielectric layer for an analog capacitor, a radio frequency (RF) capacitor, or a high-voltage capacitor should be formed to a greater thickness than t1 of FIG. 2. Accordingly, deposition processes and curing processes are performed three times or more such that n dielectric layers (DL1, DL2, . . . , and DLn) are formed between two electrodes 15 and 30, as shown in FIG. 3. We suppose that the sum of thicknesses of the n dielectric layers (DL1, DL2, . . . , and DLn) is t2 (t2>t1).
FIG. 4 graphically explains the reasons for forming dielectric layers using multiple deposition and curing processes. FIG. 4 is a graph showing the results of forming a Ta2O5 layer by a twice-performed deposition and a twice-performed curing process for applying to the conventional stand-alone memory and embedded memory.
Squares ▪ shown on the graph represents a leakage current density of a capacitor, which uses TiN deposited using physical vapor deposition (PVD) as electrodes. The capacitor is manufactured by depositing a Ta2O5 layer one time to a thickness of 150 Å through chemical vapor deposition (CVD) using a source gas and an O2 reactant gas. Circle ● represents the leakage current density of a capacitor manufactured by performing a deposition process twice and performing a curing process twice as shown in FIGS. 1 and 2. In this case, TiN deposited using PVD is also employed for electrodes, and a first Ta2O5 layer is deposited to a thickness of 90 Å by CVD using a source gas and an O2 reactant gas and is then cured using O3. Then, a second Ta2O5 layer is deposited thereon to a thickness of 60 Å by the same method and is cured using O3 such that the total thickness is 150 Å.
As shown in FIG. 4, when a dielectric layer is formed by performing dual deposition and curing processes (results represented by circles ●), the leakage current density is lowered and electrical properties are markedly improved as compared to the results of the single deposit (results represented by squares ▪).
However, if a curing process is carried out following every deposition process of dielectric layers, the manufacturing process becomes complicated, thus reducing yield. Also, because several deposition chambers and several curing chambers are required, the structure of the equipment becomes complicated. Also, in the stand-alone memory and the embedded memory, a storage node contact plug may become oxidized due to a reactant gas such as O2, H2O, H2O2, and N2O injected together with the source gas during deposition. Further, in the conventional method, it is difficult to obtain good step coverage. Thus, dielectric layers having poor step coverage cannot be applied to highly integrated semiconductor devices having a narrow interval between storage electrodes (lower electrodes of a capacitor).